This invention generally relates to photolithographic patterning of semiconductor features and more particularly to an improved method for manufacturing semiconductor features such as via-first dual damascene structures while eliminating problems caused by photoresist residue contamination including undeveloped photoresist on via sidewalls.
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been the stringent requirements placed on photolithographic processes as line width and step heights have decreased for device features. As one way to overcome such limitations, various methods have been implemented to increase the resolution performance of photoresists and to eliminate photoresist interfering effects occurring in the semiconductor wafer manufacturing process.
In the fabrication of semiconductor devices multiple levels may be required for providing a multi-level interconnect structure. During the manufacture of integrated circuits it is common to place material photoresist on top of a semiconductor wafer in desired patterns and to anisotropically etch away or otherwise remove surrounding material not covered by the resist pattern in order to produce metal interconnect lines or other desired features. During the formation of semiconductor devices it is often required that the conductive layers be interconnected through conduits in an insulating layer. Such conduits are subsequently filled with metal and commonly referred to as vias, which extend through an insulating layer between two conductive areas. Metal interconnecting lines (trench lines) are typically formed over the vias to electrically interconnect the various semiconductor devices within and between multiple levels. The damascene process is a well known semiconductor fabrication method for forming electrical interconnects between levels by forming vias and trench lines.
For example, in an exemplary process for forming dual damascene structures, a via opening is first anisotropically etched in an insulating layer also known as an inter-metal dielectric (IMD) layer. The insulating layer is typically formed over a metal or conductive area including an overlying lining or etching stop layer. After a series of photolithographic and anisotropic etching steps forming a respective via opening and overlying trench opening encompassing the via opening, the via opening and the trench opening are filled with a metal (e.g., Al, Cu) to form via and trench line portions of a dual damascene structure. The excess metal above the trench level is then removed by well known chemical-mechanical polishing (CMP) processes.
As feature sizes in anisotropic etching process have diminished, photolithographic patterning processes require activating light (radiation) of increasingly smaller wavelength. Increasingly, deep ultraviolet (DUV) photoresists with activating light source wavelengths of less than about 250 nm, for example, from about 193 nm to about 248 nm are used. Exemplary DUV photoresists, for example, include PMMA and polybutene sulfone.
One problem affecting DUV photoresist processes has been the interference of residual nitrogen-containing species, for example amides, with the DUV photoresist. Residual nitrogen-containing contamination is one of the greater concerns in the use of metal nitride layers such as silicon nitride and silicon oxynitride and metal carbide layers such as silicon carbide. For example, such layers are frequently used as a etching stop layers and silicon oxynitride as a dielectric anti-reflectance coating (DARC). The nitride layers are frequently formed by CVD process using amine and amide containing precursors which tend to diffuse into adjacent porous layers. For example, the increasing use of low-k dielectric materials, typically having a high degree of porosity, facilitates absorption and transport of contaminating chemical species. For example, it is believed that nitrogen radicals created due to the presence of nitrogen containing species, such as amines and amides, interfere with chemically amplified photoresists, for example DUV photoresists, by neutralizing the acid catalyst, thereby rendering the contaminated portion of the photoresist insoluble in the developer. As a result, residual photoresist may remain on patterned feature edges, sidewalls, or floors of features, affecting subsequent etching or metal filling processes leading to, for example, electrical open circuits or increased resistivity.
In a via-first dual damascene process, a method is disclosed for forming a via plug at least partially filling the via opening in commonly assigned co-pending application Ser. No. 10/035,690, filed Nov. 8, 2001, which is incorporated herein by reference. For example, following formation of a via opening, a via plug of polymeric material is formed by depositing an resinous layer, for example an I-line resin, to fill the via opening. The via plug is formed to at least partially fill the via opening by a plasma etch back process of the resinous layer. The via plug is intended to prevent out diffusion of contaminating species from the IMD layer to contaminate subsequently deposited DUV photoresist for trench line opening patterning. A shortcoming of the etchback process is the difficulty in forming a via plug fully filling the via opening due to the difficulty in determining etching endpoint thereby frequently forming a partially filled via opening. Another shortcoming is the via sidewalls may be damaged during the etchback process. For example, the DUV photoresist layer used for patterning the trench openings, fills the upper portion of the via opening and forms an undeveloped photoresist residue layer along a portion of the sidewalls above the via plug of the via opening during the photolithographic patterning process. The photoresist residue is believed to be caused by contaminating chemical interference (e.g., amides or amines) with the DUV photoresist exposure and development process. As a result, the upper portions of the via sidewalls above the via plug are contaminated with an undeveloped photoresist residue layer, also referred to as photoresist poisoning, which subsequently detrimentally affects etching profiles, for example, in etching the trench portion of the dual damascene structure. Consequently, subsequent metal filling processes for filling the dual damascene structure with metal, for example copper, results in poor step coverage. As a result, areas of high electrical resistance are formed thereby leading to electrical reliability problems in semiconductor devices including the formation of open circuits.
Other approaches to prevent the diffusion of contaminating nitrogen containing species from overlying etching stop or DARC layers including for example silicon oxynitride, include forming a silicon dioxide layer over the low dielectric constant IMD layer prior to forming the etching stop or DARC layers. A shortcoming of this approach is the added stresses applied to the IMD layer and the added contribution to the overall capacitance of the multi-level semiconductor device.
There is therefore a need to develop a method whereby reliable photolithographic processes may be carried out without the detrimental effects of photoresist poisoning.
It is therefore an object of the invention to provide a method in the semiconductor processing art whereby reliable photolithographic processes may be carried out without the detrimental effects of photoresist poisoning while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process.
In a first embodiment, the method includes providing a semiconductor wafer having a process surface including a first anisotropically etched opening extending through a semiconductor wafer thickness portion including an underlying dielectric insulating layer; blanket depositing a polymeric resinous layer over the semiconductor wafer process surface to include filling the first anisotropically etched opening; curing the polymeric resinous layer by exposing the polymeric resinous layer to at least one of thermal or photonic energy to initiate polymer cross linking; chemically mechanically polishing (CMP) the polymeric resinous layer to substantially remove the polymeric resinous layer thickness above the process surface; and, forming a photolithographically patterned photoresist layer over the process surface for forming a second anisotropically etched opening overlying and encompassing the first anisotropically etched opening.